SC424MLTRT【PDF 24/29 页】IC REG DL BUCK/LINEAR 28MLPQ

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SC414/SC424

Applications Information (continued)

This causes the output current to move from 6A to 0A in

4.8約, giving the minimum output capacitance require-

ment shown in the following equation.

OUT

443

OUT

Note that C

OUT

is much smaller in this example, 443糉

compared to 772糉 based on a worst-case load release. To

meet the two design criteria of minimum 443糉 and

maximum 15m?ESR, select two capacitors rated at 220糉

and 15m?ESR or less.

It is recommended that an additional small capacitor be

placed in parallel with C

OUT

in order to fi lter high frequency

switching noise.

Stability Considerations

Unstable operation is possible with adaptive on-time con-

trollers, and usually takes the form of double-pulsing or

ESR loop instability.

Double-pulsing occurs due to switching noise seen at the

FB input or because the FB ripple voltage is too low. This

causes the FB comparator to trigger prematurely after the

minimum off -time has expired. In extreme cases the noise

can cause three or more successive on-times. Double-

pulsing will result in higher ripple voltage at the output,

but in most applications it will not aff ect operation. This

form of instability can usually be avoided by providing the

FB pin with a smooth, clean ripple signal that is at least

10mVp-p, which may dictate the need to increase the ESR

of the output capacitors. It is also imperative to provide a

proper PCB layout as discussed in the Layout Guidelines

section.

Another way to eliminate doubling-pulsing is to add a

small (~ 10pF) capacitor across the upper feedback resis-

tor, as shown in Figure 13. This capacitor should be left

unpopulated unless it can be confirmed that double-

pulsing exists. Adding the C

TOP

capacitor will couple more

ripple into FB to help eliminate the problem. An optional

connection on the PCB should be available for this

capacitor.

OUT

To FB pin

TOP

Figure 13 Capacitor Coupling to FB Pin

ESR loop instability is caused by insufficient ESR. The

details of this stability issue are discussed in the ESR

Requirements section. The best method for checking sta-

bility is to apply a zero-to-full load transient and observe

the output voltage ripple envelope for overshoot and

ringing. Ringing for more than one cycle after the initial

step is an indication that the ESR should be increased.

One simple way to solve this problem is to add trace resis-

tance in the high current output path. A side eff ect of

adding trace resistance is a decrease in load regulation.

ESR Requirements

A minimum ESR is required for two reasons. One reason is

to generate enough output ripple voltage to provide

10mVp-p at the FB pin (after the resistor divider) to avoid

double-pulsing.

The second reason is to prevent instability due to insuffi -

cient ESR. The on-time control regulates the valley of the

output ripple voltage. This ripple voltage is the sum of the

two voltages. One is the ripple generated by the ESR, the

other is the ripple due to capacitive charging and dis-

charging during the switching cycle. For most applica-

tions, the total output ripple voltage is dominated by the

output capacitors, typically SP or POSCAP devices. For

stability the ESR zero of the output capacitor should be

lower than approximately one-third the switching fre-

quency. The formula for minimum ESR is shown by the

following equation.

OUT

MIN

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